Cortex-A35: Implement workaround for errata 855472

Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.

Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <[email protected]>

diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index 222c6a7fdf03323caf6a9d957e417f7e1ddfc995..0b581692f103130c44ceb85caa652f299983935b 100644 (file)
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -92,6 +92,11 @@ For Cortex-A17, the following errata build flags are defined :
 -  ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
 
+For Cortex-A35, the following errata build flags are defined :
+
+-  ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
+   CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
+
 For Cortex-A53, the following errata build flags are defined :
 
 -  ``ERRATA_A53_819472``: This applies errata 819472 workaround to all

diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h
index 06788049168815bc6c43e0720601106752ba6835..5421478d20f667033886a10b34f0f1b74a0e12b5 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a35.h
+++ b/include/lib/cpus/aarch64/cortex_a35.h
@@ -19,4 +19,11 @@
 #define CORTEX_A35_CPUECTLR_EL1                        S3_1_C15_C2_1
 #define CORTEX_A35_CPUECTLR_SMPEN_BIT          (ULL(1) << 6)
 
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A35_CPUACTLR_EL1                        S3_1_C15_C2_0
+
+#define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI      (ULL(1) << 44)
+
 #endif /* CORTEX_A35_H */

diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S
index 96e5dd3838fa5628731fe99e100c01570bb0b9ca..be3c652cca4329b2b5ff8aadc17824a6a692eb0d 100644 (file)
--- a/lib/cpus/aarch64/cortex_a35.S
+++ b/lib/cpus/aarch64/cortex_a35.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -36,12 +36,47 @@ func cortex_a35_disable_smp
        ret
 endfunc cortex_a35_disable_smp
 
+        /* ---------------------------------------------------
+        * Errata Workaround for Cortex A35 Errata #855472.
+        * This applies to revisions r0p0 of Cortex A35.
+        * Inputs:
+        * x0: variant[4:7] and revision[0:3] of current cpu.
+        * Shall clobber: x0-x17
+        * ---------------------------------------------------
+        */
+func errata_a35_855472_wa
+        /*
+         * Compare x0 against revision r0p0
+         */
+        mov    x17, x30
+        bl     check_errata_855472
+        cbz    x0, 1f
+        mrs    x1, CORTEX_A35_CPUACTLR_EL1
+        orr    x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
+        msr    CORTEX_A35_CPUACTLR_EL1, x1
+        isb
+1:
+       ret     x17
+endfunc errata_a35_855472_wa
+
+func check_errata_855472
+       mov     x1, #0x00
+       b       cpu_rev_var_ls
+endfunc check_errata_855472
+
        /* -------------------------------------------------
         * The CPU Ops reset function for Cortex-A35.
         * Clobbers: x0
         * -------------------------------------------------
         */
 func cortex_a35_reset_func
+       mov     x19, x30
+       bl      cpu_get_rev_var
+
+#if ERRATA_A35_855472
+       bl      errata_a35_855472_wa
+#endif
+
        /* ---------------------------------------------
         * Enable the SMP bit.
         * ---------------------------------------------
@@ -50,7 +85,7 @@ func cortex_a35_reset_func
        orr     x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
        msr     CORTEX_A35_CPUECTLR_EL1, x0
        isb
-       ret
+       ret     x19
 endfunc cortex_a35_reset_func
 
 func cortex_a35_core_pwr_dwn
@@ -119,6 +154,18 @@ endfunc cortex_a35_cluster_pwr_dwn
  * Errata printing function for Cortex A35. Must follow AAPCS.
  */
 func cortex_a35_errata_report
+       stp     x8, x30, [sp, #-16]!
+
+       bl      cpu_get_rev_var
+       mov     x8, x0
+
+       /*
+        * Report all errata. The revision-variant information is passed to
+        * checking functions of each errata.
+        */
+       report_errata ERRATA_A35_855472, cortex_a35, 855472
+
+       ldp     x8, x30, [sp], #16
        ret
 endfunc cortex_a35_errata_report
 #endif

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index c7e8b33a3c36467a9b8d7ed2f0ed6badb1ff6986..bfee990bb2332c5f6fde1142c80266347499fbfa 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -72,6 +72,10 @@ ERRATA_A17_852421    ?=0
 # only to revision <= r1p2 of the Cortex A17 cpu.
 ERRATA_A17_852423      ?=0
 
+# Flag to apply erratum 855472 workaround during reset. This erratum applies
+# only to revision r0p0 of the Cortex A35 cpu.
+ERRATA_A35_855472      ?=0
+
 # Flag to apply erratum 819472 workaround during reset. This erratum applies
 # only to revision <= r0p1 of the Cortex A53 cpu.
 ERRATA_A53_819472      ?=0
@@ -235,6 +239,10 @@ $(eval $(call add_define,ERRATA_A17_852421))
 $(eval $(call assert_boolean,ERRATA_A17_852423))
 $(eval $(call add_define,ERRATA_A17_852423))
 
+# Process ERRATA_A35_855472 flag
+$(eval $(call assert_boolean,ERRATA_A35_855472))
+$(eval $(call add_define,ERRATA_A35_855472))
+
 # Process ERRATA_A53_819472 flag
 $(eval $(call assert_boolean,ERRATA_A53_819472))
 $(eval $(call add_define,ERRATA_A53_819472))